1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device known as EEPROM (electrically erasable programmable read-only memory).
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows, in block form, memory cells and associated circuit components of a flash EEPROM which can erase all data stored in memory cells at one time. The circuit arrangement shown in FIG. 1 corresponds to one bit of an output signal. If the flash EEPROM is of an 8-bit output configuration, it has eight circuits each identical to that shown in FIG. 1 which are arranged parallel to each other.
The flash EEPROM has terminals PP connected to an external voltage supply Vpp for supplying the high voltage required when the EEPROM writes or erases data. The flash EEPROM also has a plurality of column address lines Y.sub.11, . . . , Y.sub.1, Y.sub.s21, . . . , Y.sub.s2j for indicating the row address of a memory cell, and a plurality of row address lines X.sub.1, . . . , X.sub.k for indicating the row address of a memory cell. In write mode, a data input line D.sub.IN supplies a memory cell which has been selected by a column address line and row address line with data "0" that indicates a high voltage of VPG for actually writing data, or with data "1" that indicates a voltage of 0 V for writing no data. A signal ER is of a high level "H" in erase mode and of a low level "L" in other modes.
An N-channel enhancement MOSFET (hereinafter referred to as "NE-MOSFET") Q.sub.Y1W for writing data has a gate controlled by the data input line D.sub.IN. The flash EEPROM also includes a plurality of NE-MOSFETs Q.sub.YS211, . . . , Q.sub.YS21j, Q.sub.Y111, . . . , Q.sub.Y1l, . . . , Q.sub.Y1jl for selecting row addresses. Memory cells M.sub.111l, . . . , M.sub.lk1l have respective drains connected in common to a digit line D.sub.11l, respective sources connected in common to a common source terminal CS, and respective gates connected respectively to the row address lines X.sub.1, . . . , X.sub.k. Memory cells M.sub.1111, . . . , M.sub.1k11 have respective drains connected in common to a digit line D.sub.111, respective sources connected in common to the common source terminal CS, and respective gates connected respectively to the row address lines X.sub.1, . . . , X.sub.k. Memory cells M.sub.11jl, . . . , M.sub.1kjl have respective drains connected in common to a digit line D.sub.1j1, respective sources connected in common to the common source terminal CS, and respective gates connected respectively to the row address lines X.sub.1, . . . , X.sub.k. Memory cells M.sub.11jl, . . . , M.sub.1kjl have respective drains connected in common to a digit line D.sub.1jl, respective sources connected in common to the common source terminal CS, and respective gates connected respectively to the row address lines X.sub.1, . . . , X.sub.k. The memory cells M.sub.111l, . . . , M.sub.1k11, M.sub.111l, . . . , M.sub.1k1l are arranged as a memory cell matrix MX.sub.1l having an output node N.sub.1l, and the memory cells M.sub.1ljl, . . . , M.sub.1kjl, M.sub.11jl, . . . , M.sub.1kjl are arranged as a memory cell matrix MX.sub.1j having an output node N.sub.1j.
In read mode, a sensing amplifier SA1 serves to detect whether a memory cell which has been selected by a row address line and a column address line stores "0" (i.e., the memory cell has written data) or "1" (i.e., the memory cell has no written data or has erased data). The sensing amplifier SA1 can amplify a change in the voltage at a data bus SC.sub.1. The sensing amplifier SA1 produces an output signal S.sub.out1 indicative of the detected result. A source switch SS applies a voltage of 0 V to the common source terminal CS in write and read modes, and an erase voltage V.sub.pp to the common source terminal CS in erase mode.
The following table shows voltages at the signal lines and nodes at the time the memory cell M.sub.1111 is selected by row and column address lines in write, erase, and read modes:
______________________________________ Node YS.sub.21 Mode PP X.sub.1 Y.sub.11 (Y.sub.21) D.sub.IN D.sub.111 CS ______________________________________ Data "0" VPG - Write 12 V 12 V 12 V 12 V VPG VTN 0 V Date "1" Erase 12 V 0 V 0 V 0 V 0 V Float- 12 V ing Read 5 V 5 V 5 V 5 V 0 V 1.5 V 0 V ______________________________________
Operation of the flash EEPROM in the above three modes will be briefly described below with reference to FIG. 1 and the above table.